The semiconductor integrated circuit (IC) industry has experienced rapid growth. In the course of IC evolution, functional density has generally increased while feature size has decreased. This scaling down process generally provides benefits by increasing production efficiency and lowering associated costs. However, the rapid growth also presents challenges in maintaining and improving performance of the devices. One method used by the industry to meet the performance demands for semiconductor devices is the adoption metal gate electrodes. One method of forming metal gate electrodes adopted by the industry is that of the gate-last or replacement gate methodology. The replacement gate architecture provides benefits such as improved work function material stability, increased ability to tune the work function metal to the device type (e.g., PMOS, NMOS), and decreased exposure of the gate electrode to high temperature processing.
However, the replacement gate methodology also presents challenges as it typically includes additional process modules such as chemical mechanical polishing (CMP) and the processing required to strip out a dummy gate that the metal gate electrode replaces. These process modules can expose the surrounding features to additional stresses. For example, the interlayer dielectric (ILD) that provides isolation between gate features can be attacked by the CMP and dummy gate removal processes causing unwanted loss of the dielectric.